This specification relates to validating memory access requests.
Graphics processing units (GPUs) may have highly concurrent accesses to random addresses and may include on-GPU hardware to perform address translation that generates addresses targeting central processing unit (CPU) dynamic random-access memory (DRAM). Similarly, some network interface cards (NICs) and solid state drives (SSDs) may perform their own address translation.
Peripheral component interconnect (PCI) address translation services (ATS) allows a device to request an address translation from an input/output memory management unit (IOMMU) and cache the translation locally on the device. Subsequent accesses to the translated range by the device can be marked as already translated and bypass the IOMMU.